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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications
A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the...
Autores principales: | , , , , , , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2021
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8037875/ https://www.ncbi.nlm.nih.gov/pubmed/33804902 http://dx.doi.org/10.3390/s21072260 |
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author | Shehzad, Khuram Verma, Deeksha Khan, Danial Ain, Qurat Ul Basim, Muhammad Kim, Sung Jin Rikan, Behnam Samadpoor Pu, Young Gun Hwang, Keum Cheol Yang, Youngoo Lee, Kang-Yoon |
author_facet | Shehzad, Khuram Verma, Deeksha Khan, Danial Ain, Qurat Ul Basim, Muhammad Kim, Sung Jin Rikan, Behnam Samadpoor Pu, Young Gun Hwang, Keum Cheol Yang, Youngoo Lee, Kang-Yoon |
author_sort | Shehzad, Khuram |
collection | PubMed |
description | A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm(2). With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply. |
format | Online Article Text |
id | pubmed-8037875 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2021 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-80378752021-04-12 A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications Shehzad, Khuram Verma, Deeksha Khan, Danial Ain, Qurat Ul Basim, Muhammad Kim, Sung Jin Rikan, Behnam Samadpoor Pu, Young Gun Hwang, Keum Cheol Yang, Youngoo Lee, Kang-Yoon Sensors (Basel) Communication A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm(2). With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply. MDPI 2021-03-24 /pmc/articles/PMC8037875/ /pubmed/33804902 http://dx.doi.org/10.3390/s21072260 Text en © 2021 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/ (https://creativecommons.org/licenses/by/4.0/) ). |
spellingShingle | Communication Shehzad, Khuram Verma, Deeksha Khan, Danial Ain, Qurat Ul Basim, Muhammad Kim, Sung Jin Rikan, Behnam Samadpoor Pu, Young Gun Hwang, Keum Cheol Yang, Youngoo Lee, Kang-Yoon A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title | A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title_full | A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title_fullStr | A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title_full_unstemmed | A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title_short | A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications |
title_sort | low-power 12-bit 20 ms/s asynchronously controlled sar adc for wave its sensor based applications |
topic | Communication |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8037875/ https://www.ncbi.nlm.nih.gov/pubmed/33804902 http://dx.doi.org/10.3390/s21072260 |
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