Cargando…
A Latency-Optimized Network-on-Chip with Rapid Bypass Channels
Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassin...
Autores principales: | Ma, Wenheng, Gao, Xiyao, Gao, Yudi, Yu, Ningmei |
---|---|
Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2021
|
Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8226511/ https://www.ncbi.nlm.nih.gov/pubmed/34072266 http://dx.doi.org/10.3390/mi12060621 |
Ejemplares similares
-
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture
por: Ma, Wenheng, et al.
Publicado: (2021) -
High-Precision Lens-Less Flow Cytometer on a Chip
por: Fang, Yuan, et al.
Publicado: (2018) -
An on-chip instrument for white blood cells classification based on a lens-less shadow imaging technique
por: Fang, Yuan, et al.
Publicado: (2017) -
A low latency and low power indirect topology for on-chip communication
por: Gulzari, Usman Ali, et al.
Publicado: (2019) -
PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs
por: Zhou, Xinbing, et al.
Publicado: (2023)