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Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC
The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
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MDPI
2021
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8306510/ https://www.ncbi.nlm.nih.gov/pubmed/34357221 http://dx.doi.org/10.3390/mi12070811 |