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Evidence of weak Anderson localization revealed by the resistivity, transverse magnetoresistance and Hall effect measured on thin Cu films deposited on mica

We report the resistivity of 5 Cu films approximately 65 nm thick, measured between 5 and 290 K, and the transverse magnetoresistance and Hall effect measured at temperatures 5 K < T < 50 K. The mean grain diameters are D = (8.9, 9.8, 20.2, 31.5, 34.7) nm, respectively. The magnetoresistance s...

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Detalles Bibliográficos
Autores principales: Díaz, Eva, Herrera, Guillermo, Oyarzún, Simón, Munoz, Raul C.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group UK 2021
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8426376/
https://www.ncbi.nlm.nih.gov/pubmed/34497283
http://dx.doi.org/10.1038/s41598-021-97210-w
Descripción
Sumario:We report the resistivity of 5 Cu films approximately 65 nm thick, measured between 5 and 290 K, and the transverse magnetoresistance and Hall effect measured at temperatures 5 K < T < 50 K. The mean grain diameters are D = (8.9, 9.8, 20.2, 31.5, 34.7) nm, respectively. The magnetoresistance signal is positive in samples where D > L/2 (where L = 39 nm is the electron mean free path in the bulk at room temperature), and negative in samples where D < L/2. The sample where D = 20.2 nm exhibits a negative magnetoresistance at B < 2 Tesla and a positive magnetoresistance at B > 3 Tesla. A negative magnetoresistance in Cu films has been considered evidence of charge transport involving weak Anderson localization. These experiments reveal that electron scattering by disordered grain boundaries found along L leads to weak Anderson localization, confirming the localization phenomenon predicted by the quantum theory of resistivity of nanometric metallic connectors. Anderson localization becomes a severe obstacle for the successful development of the circuit miniaturization effort pursued by the electronic industry, for it leads to a steep rise in the resistivity of nanometric metallic connectors with decreasing wire dimensions (D < L/2) employed in the design of Integrated Circuits.