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Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor

In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As ea...

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Autores principales: Okura, Shunsuke, Aoki, Masanori, Oyama, Tatsuya, Shirahata, Masayoshi, Fujino, Takeshi, Ishikawa, Kenichiro, Takayanagi, Isao
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8470652/
https://www.ncbi.nlm.nih.gov/pubmed/34577283
http://dx.doi.org/10.3390/s21186079
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author Okura, Shunsuke
Aoki, Masanori
Oyama, Tatsuya
Shirahata, Masayoshi
Fujino, Takeshi
Ishikawa, Kenichiro
Takayanagi, Isao
author_facet Okura, Shunsuke
Aoki, Masanori
Oyama, Tatsuya
Shirahata, Masayoshi
Fujino, Takeshi
Ishikawa, Kenichiro
Takayanagi, Isao
author_sort Okura, Shunsuke
collection PubMed
description In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As each CR pair can be used only once to make the CIS PUF resistant to the modeling attack, CR authentication with CIS can be carried out 4050 times, with basic post-processing to generate the PUF ID. If a larger number of authentications is required, advanced post-processing using Lehmer encoding can be utilized to carry out authentication [Formula: see text] times. According to the PUF performance evaluation, the authentication error rate is less than [Formula: see text] ppm. Furthermore, the area overhead of the CIS chip for the basic and advanced post-processing is only [Formula: see text] and [Formula: see text] , respectively, based on a Verilog HDL model circuit design.
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spelling pubmed-84706522021-09-27 Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor Okura, Shunsuke Aoki, Masanori Oyama, Tatsuya Shirahata, Masayoshi Fujino, Takeshi Ishikawa, Kenichiro Takayanagi, Isao Sensors (Basel) Article In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As each CR pair can be used only once to make the CIS PUF resistant to the modeling attack, CR authentication with CIS can be carried out 4050 times, with basic post-processing to generate the PUF ID. If a larger number of authentications is required, advanced post-processing using Lehmer encoding can be utilized to carry out authentication [Formula: see text] times. According to the PUF performance evaluation, the authentication error rate is less than [Formula: see text] ppm. Furthermore, the area overhead of the CIS chip for the basic and advanced post-processing is only [Formula: see text] and [Formula: see text] , respectively, based on a Verilog HDL model circuit design. MDPI 2021-09-10 /pmc/articles/PMC8470652/ /pubmed/34577283 http://dx.doi.org/10.3390/s21186079 Text en © 2021 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Okura, Shunsuke
Aoki, Masanori
Oyama, Tatsuya
Shirahata, Masayoshi
Fujino, Takeshi
Ishikawa, Kenichiro
Takayanagi, Isao
Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title_full Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title_fullStr Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title_full_unstemmed Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title_short Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor
title_sort area-efficient post-processing circuits for physically unclonable function with 2-mpixel cmos image sensor
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8470652/
https://www.ncbi.nlm.nih.gov/pubmed/34577283
http://dx.doi.org/10.3390/s21186079
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