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Low-Latency QC-LDPC Encoder Design for 5G NR
In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval...
Autores principales: | , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2021
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8470965/ https://www.ncbi.nlm.nih.gov/pubmed/34577470 http://dx.doi.org/10.3390/s21186266 |
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author | Tian, Yunke Bai, Yong Liu, Dake |
author_facet | Tian, Yunke Bai, Yong Liu, Dake |
author_sort | Tian, Yunke |
collection | PubMed |
description | In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design. |
format | Online Article Text |
id | pubmed-8470965 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2021 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-84709652021-09-27 Low-Latency QC-LDPC Encoder Design for 5G NR Tian, Yunke Bai, Yong Liu, Dake Sensors (Basel) Article In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design. MDPI 2021-09-18 /pmc/articles/PMC8470965/ /pubmed/34577470 http://dx.doi.org/10.3390/s21186266 Text en © 2021 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Tian, Yunke Bai, Yong Liu, Dake Low-Latency QC-LDPC Encoder Design for 5G NR |
title | Low-Latency QC-LDPC Encoder Design for 5G NR |
title_full | Low-Latency QC-LDPC Encoder Design for 5G NR |
title_fullStr | Low-Latency QC-LDPC Encoder Design for 5G NR |
title_full_unstemmed | Low-Latency QC-LDPC Encoder Design for 5G NR |
title_short | Low-Latency QC-LDPC Encoder Design for 5G NR |
title_sort | low-latency qc-ldpc encoder design for 5g nr |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8470965/ https://www.ncbi.nlm.nih.gov/pubmed/34577470 http://dx.doi.org/10.3390/s21186266 |
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