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A Feasible Alternative to FDSOI and FinFET: Optimization of W/La(2)O(3)/Si Planar PMOS with 14 nm Gate-Length
At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (I(off)). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performan...
| Autores principales: | , , , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2021
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8510296/ https://www.ncbi.nlm.nih.gov/pubmed/34640118 http://dx.doi.org/10.3390/ma14195721 |