A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers...

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Detalles Bibliográficos
Autores principales: Sheu, Ming-Hwa, Tsai, Chang-Ming, Tsai, Ming-Yan, Hsia, Shih-Chang, Morsalin, S. M. Salahuddin, Lin, Jin-Fa
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Communication
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8512319/
https://www.ncbi.nlm.nih.gov/pubmed/34640911
http://dx.doi.org/10.3390/s21196591

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8512319/
https://www.ncbi.nlm.nih.gov/pubmed/34640911
http://dx.doi.org/10.3390/s21196591

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