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A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fs(rms) Integrated Jitter and −251.6 dB FoM
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to av...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2021
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8623227/ https://www.ncbi.nlm.nih.gov/pubmed/34833724 http://dx.doi.org/10.3390/s21227648 |