Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In ord...

Descripción completa

Detalles Bibliográficos
Autores principales: Kim, Min-Kyeong, Choi, Yang-Kyu, Park, Jun-Young
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8778583/
https://www.ncbi.nlm.nih.gov/pubmed/35056288
http://dx.doi.org/10.3390/mi13010124
Descripción
Sumario:Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.

Ejemplares similares