Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In ord...

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Autores principales: Kim, Min-Kyeong, Choi, Yang-Kyu, Park, Jun-Young
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8778583/
https://www.ncbi.nlm.nih.gov/pubmed/35056288
http://dx.doi.org/10.3390/mi13010124
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author Kim, Min-Kyeong
Choi, Yang-Kyu
Park, Jun-Young
author_facet Kim, Min-Kyeong
Choi, Yang-Kyu
Park, Jun-Young
author_sort Kim, Min-Kyeong
collection PubMed
description Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.
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spelling pubmed-87785832022-01-22 Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs Kim, Min-Kyeong Choi, Yang-Kyu Park, Jun-Young Micromachines (Basel) Article Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules. MDPI 2022-01-13 /pmc/articles/PMC8778583/ /pubmed/35056288 http://dx.doi.org/10.3390/mi13010124 Text en © 2022 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Kim, Min-Kyeong
Choi, Yang-Kyu
Park, Jun-Young
Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title_full Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title_fullStr Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title_full_unstemmed Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title_short Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
title_sort power reduction in punch-through current-based electro-thermal annealing in gate-all-around fets
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8778583/
https://www.ncbi.nlm.nih.gov/pubmed/35056288
http://dx.doi.org/10.3390/mi13010124
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