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Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In ord...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2022
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8778583/ https://www.ncbi.nlm.nih.gov/pubmed/35056288 http://dx.doi.org/10.3390/mi13010124 |