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Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes
This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is fir...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Springer US
2022
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8854306/ https://www.ncbi.nlm.nih.gov/pubmed/35222787 http://dx.doi.org/10.1007/s11265-021-01735-2 |