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An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy
Cryptography has become one of the vital disciplines for information technology such as IoT (Internet Of Things), IIoT (Industrial Internet Of Things), I4.0 (Industry 4.0), and automotive applications. Some fundamental characteristics required for these applications are confidentiality, authenticati...
Autores principales: | , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2022
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9031777/ https://www.ncbi.nlm.nih.gov/pubmed/35458970 http://dx.doi.org/10.3390/s22082985 |
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author | Torres-Alvarado, Alan Morales-Rosales, Luis Alberto Algredo-Badillo, Ignacio López-Huerta, Francisco Lobato-Báez, Mariana López-Pimentel, Juan Carlos |
author_facet | Torres-Alvarado, Alan Morales-Rosales, Luis Alberto Algredo-Badillo, Ignacio López-Huerta, Francisco Lobato-Báez, Mariana López-Pimentel, Juan Carlos |
author_sort | Torres-Alvarado, Alan |
collection | PubMed |
description | Cryptography has become one of the vital disciplines for information technology such as IoT (Internet Of Things), IIoT (Industrial Internet Of Things), I4.0 (Industry 4.0), and automotive applications. Some fundamental characteristics required for these applications are confidentiality, authentication, integrity, and nonrepudiation, which can be achieved using hash functions. A cryptographic hash function that provides a higher level of security is SHA-3. However, in real and modern applications, hardware implementations based on FPGA for hash functions are prone to errors due to noise and radiation since a change in the state of a bit can trigger a completely different hash output than the expected one, due to the avalanche effect or diffusion, meaning that modifying a single bit changes most of the desired bits of the hash; thus, it is vital to detect and correct any error during the algorithm execution. Current hardware solutions mainly seek to detect errors but not correct them (e.g., using parity checking or scrambling). To the best of our knowledge, there are no solutions that detect and correct errors for SHA-3 hardware implementations. This article presents the design and a comparative analysis of four FPGA architectures: two without fault tolerance and two with fault tolerance, which employ Hamming Codes to detect and correct faults for SHA-3 using an Encoder and a Decoder at the step-mapping functions level. Results show that the two hardware architectures with fault tolerance can detect up to a maximum of 120 and 240 errors, respectively, for every run of KECCAK-p, which is considered the worst case. Additionally, the paper provides a comparative analysis of these architectures with other works in the literature in terms of experimental results such as frequency, resources, throughput, and efficiency. |
format | Online Article Text |
id | pubmed-9031777 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2022 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-90317772022-04-23 An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy Torres-Alvarado, Alan Morales-Rosales, Luis Alberto Algredo-Badillo, Ignacio López-Huerta, Francisco Lobato-Báez, Mariana López-Pimentel, Juan Carlos Sensors (Basel) Article Cryptography has become one of the vital disciplines for information technology such as IoT (Internet Of Things), IIoT (Industrial Internet Of Things), I4.0 (Industry 4.0), and automotive applications. Some fundamental characteristics required for these applications are confidentiality, authentication, integrity, and nonrepudiation, which can be achieved using hash functions. A cryptographic hash function that provides a higher level of security is SHA-3. However, in real and modern applications, hardware implementations based on FPGA for hash functions are prone to errors due to noise and radiation since a change in the state of a bit can trigger a completely different hash output than the expected one, due to the avalanche effect or diffusion, meaning that modifying a single bit changes most of the desired bits of the hash; thus, it is vital to detect and correct any error during the algorithm execution. Current hardware solutions mainly seek to detect errors but not correct them (e.g., using parity checking or scrambling). To the best of our knowledge, there are no solutions that detect and correct errors for SHA-3 hardware implementations. This article presents the design and a comparative analysis of four FPGA architectures: two without fault tolerance and two with fault tolerance, which employ Hamming Codes to detect and correct faults for SHA-3 using an Encoder and a Decoder at the step-mapping functions level. Results show that the two hardware architectures with fault tolerance can detect up to a maximum of 120 and 240 errors, respectively, for every run of KECCAK-p, which is considered the worst case. Additionally, the paper provides a comparative analysis of these architectures with other works in the literature in terms of experimental results such as frequency, resources, throughput, and efficiency. MDPI 2022-04-13 /pmc/articles/PMC9031777/ /pubmed/35458970 http://dx.doi.org/10.3390/s22082985 Text en © 2022 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Torres-Alvarado, Alan Morales-Rosales, Luis Alberto Algredo-Badillo, Ignacio López-Huerta, Francisco Lobato-Báez, Mariana López-Pimentel, Juan Carlos An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title | An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title_full | An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title_fullStr | An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title_full_unstemmed | An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title_short | An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy |
title_sort | sha-3 hardware architecture against failures based on hamming codes and triple modular redundancy |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9031777/ https://www.ncbi.nlm.nih.gov/pubmed/35458970 http://dx.doi.org/10.3390/s22082985 |
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