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The effect of excess selenium on the opto-electronic properties of Cu(2)ZnSnSe(4) prepared from Cu–Sn alloy precursors

For the fabrication of a kesterite-type CZTSe absorber material, stacked elemental-alloy layers (SEAL) precursor consisting of Cu–Sn alloy and elemental Zn layers offer the possibility of enhanced process control due to their advantages such as improvement of material homogeneity and suppression of...

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Detalles Bibliográficos
Autores principales: Taskesen, Teoman, Pareek, Devendra, Neerken, Janet, Schoneberg, Johannes, Hirwa, Hippolyte, Nowak, David, Parisi, Jürgen, Gütay, Levent
Formato: Online Artículo Texto
Lenguaje:English
Publicado: The Royal Society of Chemistry 2019
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9065798/
https://www.ncbi.nlm.nih.gov/pubmed/35515521
http://dx.doi.org/10.1039/c9ra02779c
Descripción
Sumario:For the fabrication of a kesterite-type CZTSe absorber material, stacked elemental-alloy layers (SEAL) precursor consisting of Cu–Sn alloy and elemental Zn layers offer the possibility of enhanced process control due to their advantages such as improvement of material homogeneity and suppression of the commonly observed Sn loss. In this study, the impact of selenium amounts during the annealing of a SEAL-type precursor with the configuration of Zn/Cu–Sn/Zn was demonstrated. The obtained results demonstrate how the selenium amount can indirectly be used to influence the absorber composition in the described annealing process and its direct impact on the opto-electronic properties of solar cells. This occurs due to the placement of elemental Sn in the vicinity of the sample during annealing that acts as a further source of SnSe(2) vapor during the high-temperature stage of the process depending on the degree of selenium excess. The results show that higher selenium amount increases the band gap of kesterite; this is directly accompanied by a shift of the defect activation energies. Optimization of this effect can lead to widening of the space-charge width up to 400 nm, which improves the charge carrier collection. The described optimization strategy leads to device efficiencies above 11%.