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FPGA-based systolic deconvolution architecture for upsampling

A deconvolution accelerator is proposed to upsample n × n input to 2n × 2n output by convolving with a k × k kernel. Its architecture avoids the need for insertion and padding of zeros and thus eliminates the redundant computations to achieve high resource efficiency with reduced number of multiplie...

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Autores principales: Joseph Raj, Alex Noel, Cai, Lianhong, Li, Wei, Zhuang, Zhemin, Tjahjadi, Tardi
Formato: Online Artículo Texto
Lenguaje:English
Publicado: PeerJ Inc. 2022
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9138038/
https://www.ncbi.nlm.nih.gov/pubmed/35634123
http://dx.doi.org/10.7717/peerj-cs.973
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author Joseph Raj, Alex Noel
Cai, Lianhong
Li, Wei
Zhuang, Zhemin
Tjahjadi, Tardi
author_facet Joseph Raj, Alex Noel
Cai, Lianhong
Li, Wei
Zhuang, Zhemin
Tjahjadi, Tardi
author_sort Joseph Raj, Alex Noel
collection PubMed
description A deconvolution accelerator is proposed to upsample n × n input to 2n × 2n output by convolving with a k × k kernel. Its architecture avoids the need for insertion and padding of zeros and thus eliminates the redundant computations to achieve high resource efficiency with reduced number of multipliers and adders. The architecture is systolic and governed by a reference clock, enabling the sequential placement of the module to represent a pipelined decoder framework. The proposed accelerator is implemented on a Xilinx XC7Z020 platform, and achieves a performance of 3.641 giga operations per second (GOPS) with resource efficiency of 0.135 GOPS/DSP for upsampling 32 × 32 input to 256 × 256 output using a 3 × 3 kernel at 200 MHz. Furthermore, its high peak signal to noise ratio of almost 80 dB illustrates that the upsampled outputs of the bit truncated accelerator are comparable to IEEE double precision results.
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spelling pubmed-91380382022-05-28 FPGA-based systolic deconvolution architecture for upsampling Joseph Raj, Alex Noel Cai, Lianhong Li, Wei Zhuang, Zhemin Tjahjadi, Tardi PeerJ Comput Sci Artificial Intelligence A deconvolution accelerator is proposed to upsample n × n input to 2n × 2n output by convolving with a k × k kernel. Its architecture avoids the need for insertion and padding of zeros and thus eliminates the redundant computations to achieve high resource efficiency with reduced number of multipliers and adders. The architecture is systolic and governed by a reference clock, enabling the sequential placement of the module to represent a pipelined decoder framework. The proposed accelerator is implemented on a Xilinx XC7Z020 platform, and achieves a performance of 3.641 giga operations per second (GOPS) with resource efficiency of 0.135 GOPS/DSP for upsampling 32 × 32 input to 256 × 256 output using a 3 × 3 kernel at 200 MHz. Furthermore, its high peak signal to noise ratio of almost 80 dB illustrates that the upsampled outputs of the bit truncated accelerator are comparable to IEEE double precision results. PeerJ Inc. 2022-05-11 /pmc/articles/PMC9138038/ /pubmed/35634123 http://dx.doi.org/10.7717/peerj-cs.973 Text en ©2022 Joseph Raj et al. https://creativecommons.org/licenses/by/4.0/This is an open access article distributed under the terms of the Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0/) , which permits unrestricted use, distribution, reproduction and adaptation in any medium and for any purpose provided that it is properly attributed. For attribution, the original author(s), title, publication source (PeerJ Computer Science) and either DOI or URL of the article must be cited.
spellingShingle Artificial Intelligence
Joseph Raj, Alex Noel
Cai, Lianhong
Li, Wei
Zhuang, Zhemin
Tjahjadi, Tardi
FPGA-based systolic deconvolution architecture for upsampling
title FPGA-based systolic deconvolution architecture for upsampling
title_full FPGA-based systolic deconvolution architecture for upsampling
title_fullStr FPGA-based systolic deconvolution architecture for upsampling
title_full_unstemmed FPGA-based systolic deconvolution architecture for upsampling
title_short FPGA-based systolic deconvolution architecture for upsampling
title_sort fpga-based systolic deconvolution architecture for upsampling
topic Artificial Intelligence
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9138038/
https://www.ncbi.nlm.nih.gov/pubmed/35634123
http://dx.doi.org/10.7717/peerj-cs.973
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