Cargando…

A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications

This paper presents an on-chip implementation of an analog processor-in-memory (PIM)-based convolutional neural network (CNN) in a biosensor. The operator was designed with low power to implement CNN as an on-chip device on the biosensor, which consists of plates of 32 × 32 material. In this paper,...

Descripción completa

Detalles Bibliográficos
Autores principales: Byun, Sung-June, Kim, Dong-Gyun, Park, Kyung-Do, Choi, Yeun-Jin, Kumar, Pervesh, Ali, Imran, Kim, Dong-Gyu, Yoo, June-Mo, Huh, Hyung-Ki, Jung, Yeon-Jae, Kim, Seok-Kee, Pu, Young-Gun, Lee, Kang-Yoon
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9229394/
https://www.ncbi.nlm.nih.gov/pubmed/35746337
http://dx.doi.org/10.3390/s22124555
Descripción
Sumario:This paper presents an on-chip implementation of an analog processor-in-memory (PIM)-based convolutional neural network (CNN) in a biosensor. The operator was designed with low power to implement CNN as an on-chip device on the biosensor, which consists of plates of 32 × 32 material. In this paper, 10T SRAM-based analog PIM, which performs multiple and average (MAV) operations with multiplication and accumulation (MAC), is used as a filter to implement CNN at low power. PIM proceeds with MAV operations, with feature extraction as a filter, using an analog method. To prepare the input feature, an input matrix is formed by scanning a 32 × 32 biosensor based on a digital controller operating at 32 MHz frequency. Memory reuse techniques were applied to the analog SRAM filter, which is the core of low power implementation, and in order to accurately grasp the MAC operational efficiency and classification, we modeled and trained numerous input features based on biosignal data, confirming the classification. When the learned weight data was input, 19 mW of power was consumed during analog-based MAC operation. The implementation showed an energy efficiency of 5.38 TOPS/W and was differentiated through the implementation of 8 bits of high resolution in the 180 nm CMOS process.