Layer-by-layer epitaxy of multi-layer MoS(2) wafers

The 2D semiconductor of MoS(2) has great potential for advanced electronics technologies beyond silicon. So far, high-quality monolayer MoS(2) wafers have been available and various demonstrations from individual transistors to integrated circuits have also been shown. In addition to the monolayer, multilayers have narrower band gaps but improved carrier mobilities and current capacities over the monolayer. However, achieving high-quality multi-layer MoS(2) wafers remains a challenge. Here we report the growth of high-quality multi-layer MoS(2) 4-inch wafers via the layer-by-layer epitaxy process. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to six. Systematic evaluations on the atomic structures and electronic properties were carried out for achieved wafers with different layer numbers. Significant improvements in device performances were found in thicker-layer field-effect transistors (FETs), as expected. For example, the average field-effect mobility (μ(FE)) at room temperature (RT) can increase from ∼80 cm(2)·V(–1)·s(–1) for monolayers to ∼110/145 cm(2)·V(–1)·s(–1) for bilayer/trilayer devices. The highest RT μ(FE) of 234.7 cm(2)·V(–1)·s(–1) and record-high on-current densities of 1.70 mA·μm(–1) at V(ds) = 2 V were also achieved in trilayer MoS(2) FETs with a high on/off ratio of >10(7). Our work hence moves a step closer to practical applications of 2D MoS(2) in electronics.