Cargando…
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors
In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss. The SHA-256 algorithm is used to tackle these requiremen...
Autores principales: | Algredo-Badillo, Ignacio, Morales-Sandoval, Miguel, Medina-Santiago, Alejandro, Hernández-Gracidas, Carlos Arturo, Lobato-Baez, Mariana, Morales-Rosales, Luis Alberto |
---|---|
Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2022
|
Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9269824/ https://www.ncbi.nlm.nih.gov/pubmed/35808523 http://dx.doi.org/10.3390/s22135028 |
Ejemplares similares
-
An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy
por: Torres-Alvarado, Alan, et al.
Publicado: (2022) -
Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models
por: Torres-Alvarado, Alan, et al.
Publicado: (2022) -
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES
por: Algredo-Badillo, Ignacio, et al.
Publicado: (2021) -
Compact FPGA hardware architecture for public key encryption in embedded devices
por: Rodríguez-Flores, Luis, et al.
Publicado: (2018) -
CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
por: Medina-Santiago, Alejandro, et al.
Publicado: (2021)