Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvemen...

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Detalles Bibliográficos
Autores principales: Chen, Kun, Yang, Jingwen, Liu, Tao, Wang, Dawei, Xu, Min, Wu, Chunlei, Wang, Chen, Xu, Saisheng, Zhang, David Wei, Liu, Wenchao
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9321815/
https://www.ncbi.nlm.nih.gov/pubmed/35888897
http://dx.doi.org/10.3390/mi13071080

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