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Real-Time Regulation of Beam-Based Feedback: Implementing an FPGA Solution for a Continuous Wave Linear Accelerator

Control applications targeting fast industrial processes rely on real-time feasible implementations. One of such applications is the stabilization of an electron bunch arrival time in the context of a linear accelerator. In the past, only the electric field accelerating the electron bunches was acti...

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Detalles Bibliográficos
Autores principales: Maalberg, Andrei, Kuntzsch, Michael, Petlenkov, Eduard
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9412282/
https://www.ncbi.nlm.nih.gov/pubmed/36015995
http://dx.doi.org/10.3390/s22166236
Descripción
Sumario:Control applications targeting fast industrial processes rely on real-time feasible implementations. One of such applications is the stabilization of an electron bunch arrival time in the context of a linear accelerator. In the past, only the electric field accelerating the electron bunches was actively controlled in order to implicitly stabilize the accelerated electron beam. Nowadays, beam properties are specifically measured at a target position and then stabilized by a dedicated feedback loop acting on the accelerating structures. This dedicated loop is usually referred to as a beam-based feedback (BBF). Following this, the control system of the electron linear accelerator for beams with high brilliance and low emittance (ELBE) is planned to be upgraded by the BBF, and the problem of implementing a designed control algorithm becomes highly relevant. In this work, we propose a real-time feasible implementation of a high-order [Formula: see text] regulator based on a field-programmable gate array (FPGA). By presenting simulation and synthesis results made in hardware description language (HDL) VHDL, we show that the proposed digital solution is fast enough to cover the bunch repetition rates frequently used at ELBE, such as 100 [Formula: see text]. Finally, we verify the implementation by using a dedicated FPGA testbench.