Design and circuit simulation of nanoscale vacuum channel transistors

Nanoscale vacuum channel transistors (NVCTs) are promising candidates in electronics due to their high frequency, fast response and high reliability, and have attracted considerable attention for structural design and optimization. However, conventional modeling for vacuum devices tends to focus on the work function or electric field distribution for an individual structure. Therefore, it is desirable for a new simulation method to explore the function circuits of NVCTs, e.g. high-speed logic circuits. In this study, a complete simulation of the fabrication, structure design and circuit simulation of NVCTs is demonstrated. First, the fabrication process was designed to be compatible with current semiconductor technology. Then, the “fabricated” structure was directly employed to investigate the influence of the structure parameters on the electrical performance. Furthermore, we explore the possibility of implementing an invert circuit with a single optimal NVCT. To the best of our knowledge, this is the first demonstration of a vacuum-state invertor with a circuit-simulation module in which NVCT functions as a conventional triode or FET. These simulation results illustrate the feasibility of integrating NVCTs into functional circuits and provide a theoretical method for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.