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A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage s...

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Autores principales: Palomeque-Mangut, David, Rodríguez-Vázquez, Ángel, Delgado-Restituto, Manuel
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9460620/
https://www.ncbi.nlm.nih.gov/pubmed/36080888
http://dx.doi.org/10.3390/s22176429
_version_ 1784786791833796608
author Palomeque-Mangut, David
Rodríguez-Vázquez, Ángel
Delgado-Restituto, Manuel
author_facet Palomeque-Mangut, David
Rodríguez-Vázquez, Ángel
Delgado-Restituto, Manuel
author_sort Palomeque-Mangut, David
collection PubMed
description This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of [Formula: see text]   [Formula: see text] [Formula: see text] [Formula: see text]. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.
format Online
Article
Text
id pubmed-9460620
institution National Center for Biotechnology Information
language English
publishDate 2022
publisher MDPI
record_format MEDLINE/PubMed
spelling pubmed-94606202022-09-10 A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process Palomeque-Mangut, David Rodríguez-Vázquez, Ángel Delgado-Restituto, Manuel Sensors (Basel) Article This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of [Formula: see text]   [Formula: see text] [Formula: see text] [Formula: see text]. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current. MDPI 2022-08-26 /pmc/articles/PMC9460620/ /pubmed/36080888 http://dx.doi.org/10.3390/s22176429 Text en © 2022 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Palomeque-Mangut, David
Rodríguez-Vázquez, Ángel
Delgado-Restituto, Manuel
A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title_full A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title_fullStr A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title_full_unstemmed A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title_short A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
title_sort fully integrated, power-efficient, 0.07–2.08 ma, high-voltage neural stimulator in a standard cmos process
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9460620/
https://www.ncbi.nlm.nih.gov/pubmed/36080888
http://dx.doi.org/10.3390/s22176429
work_keys_str_mv AT palomequemangutdavid afullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess
AT rodriguezvazquezangel afullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess
AT delgadorestitutomanuel afullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess
AT palomequemangutdavid fullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess
AT rodriguezvazquezangel fullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess
AT delgadorestitutomanuel fullyintegratedpowerefficient007208mahighvoltageneuralstimulatorinastandardcmosprocess