A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique

In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and...

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Autores principales: Guo, Zhongjie, Li, Chen, Xu, Ruiming, Cheng, Xinqi, Su, Changxu, Wu, Longsheng
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2022
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9503995/
https://www.ncbi.nlm.nih.gov/pubmed/36146399
http://dx.doi.org/10.3390/s22187050
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author Guo, Zhongjie
Li, Chen
Xu, Ruiming
Cheng, Xinqi
Su, Changxu
Wu, Longsheng
author_facet Guo, Zhongjie
Li, Chen
Xu, Ruiming
Cheng, Xinqi
Su, Changxu
Wu, Longsheng
author_sort Guo, Zhongjie
collection PubMed
description In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and bottom plates of the storage capacitor while cooperate positive feedback capacitor dynamically compensates for the charge loss of the sampling phase and the holding phase. Using the proposed circuit, after the post-layout simulation verification, the SNR of 128 stage accumulation can be improved by as much as 20.9 dB.
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spelling pubmed-95039952022-09-24 A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique Guo, Zhongjie Li, Chen Xu, Ruiming Cheng, Xinqi Su, Changxu Wu, Longsheng Sensors (Basel) Article In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and bottom plates of the storage capacitor while cooperate positive feedback capacitor dynamically compensates for the charge loss of the sampling phase and the holding phase. Using the proposed circuit, after the post-layout simulation verification, the SNR of 128 stage accumulation can be improved by as much as 20.9 dB. MDPI 2022-09-17 /pmc/articles/PMC9503995/ /pubmed/36146399 http://dx.doi.org/10.3390/s22187050 Text en © 2022 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Guo, Zhongjie
Li, Chen
Xu, Ruiming
Cheng, Xinqi
Su, Changxu
Wu, Longsheng
A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title_full A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title_fullStr A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title_full_unstemmed A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title_short A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
title_sort high snr improvement cmos analog accumulator with charge compensation technique
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9503995/
https://www.ncbi.nlm.nih.gov/pubmed/36146399
http://dx.doi.org/10.3390/s22187050
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