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A High SNR Improvement CMOS Analog Accumulator with Charge Compensation Technique
In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and...
| Autores principales: | , , , , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
MDPI
2022
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9503995/ https://www.ncbi.nlm.nih.gov/pubmed/36146399 http://dx.doi.org/10.3390/s22187050 |