Detector Processor for a 5G Base Station

Nonlinear soft bit detection is essential for the uplink receivers of 5G base stations, especially for users around the cell edge. However, its throughput and computing complexity are always challenges for both research and industry. A low-cost and low-power parallel implementation of a soft-output detector based on sorted QR decomposition (SQRD) and the K-best breadth-first search algorithm is thus proposed to reduce computational complexity and latency. In addition, to save area and reduce latency, two improvement methods are used: (1) reduce the computing cost by saturating and truncating large values during PED computing and (2) reduce the sorting cost by using the binary bit sorting method for a reduced sample set with finite accuracy. Furthermore, a pipelined VLSI architecture is designed using 28-nm digital CMOS technology offered by Semiconductor Manufacturing International Corporation (SMIC). It can achieve a peak throughput of 6400 Mbps while consuming 153 K gates (including all flip-flops) for SMIC’s 28-nm technology and running at 800 MHz, a 32% cost reduction compared with the published reference design.