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Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders
Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
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F1000 Research Limited
2022
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9677420/ https://www.ncbi.nlm.nih.gov/pubmed/36451662 http://dx.doi.org/10.12688/f1000research.73404.2 |