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FPGA Implementation of Efficient CFAR Algorithm for Radar Systems
The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and vari...
Autores principales: | , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2023
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9861839/ https://www.ncbi.nlm.nih.gov/pubmed/36679752 http://dx.doi.org/10.3390/s23020954 |
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author | Sim, Yunseong Heo, Jinmoo Jung, Yongchul Lee, Seongjoo Jung, Yunho |
author_facet | Sim, Yunseong Heo, Jinmoo Jung, Yongchul Lee, Seongjoo Jung, Yunho |
author_sort | Sim, Yunseong |
collection | PubMed |
description | The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 [Formula: see text] s to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation. |
format | Online Article Text |
id | pubmed-9861839 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2023 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-98618392023-01-22 FPGA Implementation of Efficient CFAR Algorithm for Radar Systems Sim, Yunseong Heo, Jinmoo Jung, Yongchul Lee, Seongjoo Jung, Yunho Sensors (Basel) Article The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 [Formula: see text] s to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation. MDPI 2023-01-13 /pmc/articles/PMC9861839/ /pubmed/36679752 http://dx.doi.org/10.3390/s23020954 Text en © 2023 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Sim, Yunseong Heo, Jinmoo Jung, Yongchul Lee, Seongjoo Jung, Yunho FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title | FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title_full | FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title_fullStr | FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title_full_unstemmed | FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title_short | FPGA Implementation of Efficient CFAR Algorithm for Radar Systems |
title_sort | fpga implementation of efficient cfar algorithm for radar systems |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9861839/ https://www.ncbi.nlm.nih.gov/pubmed/36679752 http://dx.doi.org/10.3390/s23020954 |
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