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Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks
Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature e...
Autores principales: | , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
Nature Publishing Group UK
2023
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9889761/ https://www.ncbi.nlm.nih.gov/pubmed/36720868 http://dx.doi.org/10.1038/s41467-023-36270-0 |
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author | Kim, Ik-Jyae Kim, Min-Kyu Lee, Jang-Sik |
author_facet | Kim, Ik-Jyae Kim, Min-Kyu Lee, Jang-Sik |
author_sort | Kim, Ik-Jyae |
collection | PubMed |
description | Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically. |
format | Online Article Text |
id | pubmed-9889761 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2023 |
publisher | Nature Publishing Group UK |
record_format | MEDLINE/PubMed |
spelling | pubmed-98897612023-02-02 Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks Kim, Ik-Jyae Kim, Min-Kyu Lee, Jang-Sik Nat Commun Article Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically. Nature Publishing Group UK 2023-01-31 /pmc/articles/PMC9889761/ /pubmed/36720868 http://dx.doi.org/10.1038/s41467-023-36270-0 Text en © The Author(s) 2023 https://creativecommons.org/licenses/by/4.0/Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/ (https://creativecommons.org/licenses/by/4.0/) . |
spellingShingle | Article Kim, Ik-Jyae Kim, Min-Kyu Lee, Jang-Sik Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title | Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title_full | Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title_fullStr | Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title_full_unstemmed | Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title_short | Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
title_sort | highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9889761/ https://www.ncbi.nlm.nih.gov/pubmed/36720868 http://dx.doi.org/10.1038/s41467-023-36270-0 |
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