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Hardware-Based Architecture for DNN Wireless Communication Models
Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted at the MIMO OFDM transmitter. It degrades the sign...
Autores principales: | , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2023
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9921442/ https://www.ncbi.nlm.nih.gov/pubmed/36772340 http://dx.doi.org/10.3390/s23031302 |
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author | Tran, Van Duy Lam, Duc Khai Tran, Thi Hong |
author_facet | Tran, Van Duy Lam, Duc Khai Tran, Thi Hong |
author_sort | Tran, Van Duy |
collection | PubMed |
description | Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted at the MIMO OFDM transmitter. It degrades the signal detection and channel estimation performance at the MIMO OFDM receiver. In this paper, three deep neural network (DNN) models are proposed to solve the problem of non-linear distortions introduced by the power amplifier (PA) of the transmitters and replace the conventional digital signal processing (DSP) modules at the receivers in 2 × 2 MIMO OFDM and 4 × 4 MIMO OFDM systems. Proposed model type I uses the DNN model to de-map the signals at the receiver. Proposed model type II uses the DNN model to learn and filter out the channel noises at the receiver. Proposed model type III uses the DNN model to de-map and detect the signals at the receiver. All three model types attempt to solve the non-linear problem. The robust bit error rate (BER) performances of the proposed receivers are achieved through the software and hardware implementation results. In addition, we have also implemented appropriate hardware architectures for the proposed DNN models using special techniques, such as quantization and pipeline to check the feasibility in practice, which recent studies have not done. Our hardware architectures are successfully designed and implemented on the Virtex 7 vc709 FPGA board. |
format | Online Article Text |
id | pubmed-9921442 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2023 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-99214422023-02-12 Hardware-Based Architecture for DNN Wireless Communication Models Tran, Van Duy Lam, Duc Khai Tran, Thi Hong Sensors (Basel) Article Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted at the MIMO OFDM transmitter. It degrades the signal detection and channel estimation performance at the MIMO OFDM receiver. In this paper, three deep neural network (DNN) models are proposed to solve the problem of non-linear distortions introduced by the power amplifier (PA) of the transmitters and replace the conventional digital signal processing (DSP) modules at the receivers in 2 × 2 MIMO OFDM and 4 × 4 MIMO OFDM systems. Proposed model type I uses the DNN model to de-map the signals at the receiver. Proposed model type II uses the DNN model to learn and filter out the channel noises at the receiver. Proposed model type III uses the DNN model to de-map and detect the signals at the receiver. All three model types attempt to solve the non-linear problem. The robust bit error rate (BER) performances of the proposed receivers are achieved through the software and hardware implementation results. In addition, we have also implemented appropriate hardware architectures for the proposed DNN models using special techniques, such as quantization and pipeline to check the feasibility in practice, which recent studies have not done. Our hardware architectures are successfully designed and implemented on the Virtex 7 vc709 FPGA board. MDPI 2023-01-23 /pmc/articles/PMC9921442/ /pubmed/36772340 http://dx.doi.org/10.3390/s23031302 Text en © 2023 by the authors. https://creativecommons.org/licenses/by/4.0/Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Tran, Van Duy Lam, Duc Khai Tran, Thi Hong Hardware-Based Architecture for DNN Wireless Communication Models |
title | Hardware-Based Architecture for DNN Wireless Communication Models |
title_full | Hardware-Based Architecture for DNN Wireless Communication Models |
title_fullStr | Hardware-Based Architecture for DNN Wireless Communication Models |
title_full_unstemmed | Hardware-Based Architecture for DNN Wireless Communication Models |
title_short | Hardware-Based Architecture for DNN Wireless Communication Models |
title_sort | hardware-based architecture for dnn wireless communication models |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9921442/ https://www.ncbi.nlm.nih.gov/pubmed/36772340 http://dx.doi.org/10.3390/s23031302 |
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