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481por Hallmann, Steffen“…The task of the fast HLT1 is to reduce the rate of triggered events such that the CPU time available in HLT2 is sufficient to trigger on particles formed by combinations of tracks.…”
Publicado 2013
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482por Kirianov, Andrey“…This study was aimed at improving resource usage for CPU-only sites by reducing the data stage-out overhead.…”
Publicado 2021
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483“…Low-cost SMP (Symmetric Multi-Processor) systems have become generallyavailable since 1998; they provide substantial CPU and I/O capacity along with a memory that is shared by all processors. …”
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484“…Those CPU's that developed in the intrasplenic-implanted marrow stroma yielded an. …”
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485por Hamdan, Jameel N., Sierra-Fonseca, Jorge A., Flores, Rodolfo J., Saucedo, Sigifredo, Miranda-Arango, Manuel, O’Dell, Laura E., Gosselink, Kristin L.“…Increased NMDAR, D2, and ALPHA expression was observed in the NAc and CPu following MatSep; D2 and ALPHA levels were also elevated in the mPFC, along with DAT. …”
Publicado 2022
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486por Schindler, H“…The upgrade of the LHCb experiment, with its installation scheduled for the second long shutdown (LS2) of the Large Hadron Collider (LHC), will transform the data acquisition and processing architecture to a triggerless readout at 40 MHz with subsequent software-based event selection in a CPU farm. In this contribution, an overview of the detector technology options under consideration and the associated challenges is given and selected highlights of the ongoing R&D programme are presented…”
Publicado 2013
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487por Pachot, Franck“…Currently in beta, this scales the database applications by avoiding the CPU context switches between the procedural code and the persistence layer. …”
Publicado 2019
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488por CMS Collaboration“…It also reports Run-3 HLT menu timing in the context of heterogeneous HLT farm deploying CPU and GPU. Performance of tracking, jet, missing transverse energy, b-tagged jet, hadronic tau and muon is reported in the first part of this note.…”
Publicado 2021
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489por Dima, M“…Routines based on this approach are over 3000 times faster than the traditional iterative procedures, yielding a 60fold increase in alignment resolution for the same amount of CPU time.…”
Publicado 2001
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490por Lamanna, M“…The main technical points are the use of Intel-based Linux PCs for both the I/O and the CPU intensive tasks, and the use of an object data base to store all the data.…”
Publicado 2001
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491“…This approach provides very high numerical stability and CPU efficiency. We find that the scale choice adopted in ATLAS simulations underestimates the tTbB background by a factor two and introduce a new dynamical scale that stabilises the perturbative predictions. …”
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492por Frederix, Rikkert, Frixione, Stefano, Hirschi, Valentin, Maltoni, Fabio, Pittau, Roberto, Torrielli, Paolo“…These are obtained through a process-independent technique that allows aMC@NLO to compute scale and PDF uncertainties in a fully automated way and at no extra CPU-time cost…”
Publicado 2011
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493por Seiss, Todd“…However, the HTT is instead a co-processor to the CPU-based Event Filter (EF) trigger, providing regional tracking at the full 1 MHz EF input event rate as well as full-event tracking on request at 100 kHz. …”
Publicado 2018
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494“…We also show a comparison of the performance on CPU and GPU implementations, demonstrating the power of algorithmic parallelization in the coming era of heterogeneous computing in high energy physics.…”
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495“…The simulation is then performed using the VegasFlow and PDFFlow libraries which deploy automatically the full simulation on systems with different hardware acceleration capabilities, such as multi-threading CPU, single-GPU and multi-GPU setups. We show some preliminary results for leading-order simulations on different hardware configurations.…”
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496por Binko, P“…The current MonteCarlo simulation program based on the GEANT3.21 package requires about 12 s to produce an average event (all CPU times are normalised to a 1000 MIPS processor). …”
Publicado 1998
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497“…This platform from Intel® hosts a general Xeon® CPU and a high performance Arria® 10 FPGA inside a multi-chip package linked via a high speed and low latency link. …”
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498por Hernández Arteaga, Dra. Isabel, Suárez Muñoz, Mtro. Jorge Andrés, Navarro Bastidas, Mtro. Martín Emilio“…Miguel Figueroa-Saavedra RuizDirectorCPU-e, Revista de Investigación Educativa Recibido: 20 de enero de 2016Aceptado: 08 de junio de 2016…”
Publicado 2016
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499por Li, Liwei, Bum-Erdene, Khuchtumur, Baenziger, Peter H., Rosen, Joshua J., Hemmert, Jamison R., Nellis, Joy A., Pierce, Marlon E., Meroueh, Samy O.“…In addition, we have scored the complexes with more intensive GBSA and PBSA approaches requiring an additional 120 000 cpu-hours on the TeraGrid. We constructed a simple interface to enable users to view top-ranking molecules and access purchasing and other information for further experimental exploration.…”
Publicado 2010
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500“…The reconstruction time achieved using spherical basis functions on a GPU was 4.3 times faster than the Central Processing Unit (CPU) and 2.5 times faster than a CPU-multi-core parallel implementation using eight cores. …”
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