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2961por Wang, Zongshan, Ding, Hongwei, Yang, Jingjing, Hou, Peng, Dhiman, Gaurav, Wang, Jie, Yang, Zhijun, Li, Aishan“…To validate the performance of OPLSSA, comparative experiments are conducted based on 23 widely used benchmark functions and 30 IEEE CEC2017 benchmark problems. Compared with some well-established algorithms, OPLSSA performs better in most of the benchmark problems.…”
Publicado 2022
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Online Artículo Texto -
2962
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2963por Deng, Yang, Qin, Hang-Yu, Zhou, Yan-Yan, Liu, Hong-Hong, Jiang, Yong, Liu, Jian-Ping, Bao, Ji“…Eligible papers were identified from PubMed and IEEE up to April 13, 2022. Through the comparison of these articles, the application status of AI technology in the diagnosis of gastric cancer was summarized, including application types, application scenarios, advantages and limitations. …”
Publicado 2022
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Online Artículo Texto -
2964por Liu, Yihao, Carass, Aaron, Zuo, Lianrui, He, Yufan, Han, Shuo, Gregori, Lorenzo, Murray, Sean, Mishra, Rohit, Lei, Jianqin, Calabresi, Peter A., Saidha, Shiv, Prince, Jerry L.Enlace del recurso
Publicado 2022
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Online Artículo Texto -
2965
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2966
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2967
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2968por Weik, Martin H“…In 1984, the Institute of Electrical and Electronic Engineers published IEEE Standard 812-1984, Definitions of Terms Relating to Fiber Optics. …”
Publicado 1997
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2969“…Review of earlier Edition (A.J. van der Schaft, IEEE Control System Magazine, 2005 ) This book can be read on many different levels and has been described as a “delightful book that will be valuable for both the control community and researchers” .…”
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2970
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2971
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2972
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2973
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2974“…Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.…”
Enlace del recurso
Enlace del recurso
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2975
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2976
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2977
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2978
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2979
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2980