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4481por Strebler, Thomas“…The upgrade to the High-Luminosity LHC (HL-LHC), with its increase to 140-200 proton-proton collisions per bunch crossing, poses formidable challenges for track reconstruction. …”
Publicado 2022
Enlace del recurso
Enlace del recurso
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4482por Dutta, Irene“…Finally, this thesis also discusses the planned MIP Timing Detector (MTD) upgrade for CMS at the HL-LHC. The MTD will be a time-of-flight (TOF) detector, designed to provide a precision timing information for charged particles using SiPMs + LYSO scintillating crystals, with a time resolution of $\sim$30 ps. …”
Publicado 2022
Enlace del recurso
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4483por Papadopoulos, Alkiviadis“…The CROCv1 front-end (FE) chip was designed by the RD53 Collaboration for the CMS Phase-2 Inner Tracker Upgrade. It is designed to cope with the extreme radiation and hit rates of the HL-LHC and it is based on the 65\,nm CMOS technology and a novel analog FE design featuring linear charge to Time-over-Threshold conversion. …”
Publicado 2022
Enlace del recurso
Enlace del recurso
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4484por Dutta, Irene“…Finally, this thesis also discusses the planned MIP Timing Detector (MTD) upgrade for CMS at the HL-LHC. The MTD will be a time-of-flight (TOF) detector, designed to provide a precision timing information for charged particles using SiPMs + LYSO scintillating crystals, with a time resolution of ∼30 ps. …”
Publicado 2022
Enlace del recurso
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4485por Tian, Yusong“…In the ATLAS detector upgrade for the High-Luminosity LHC (HL-LHC), the current Inner Detector will be upgraded to an all-silicon Inner Tracker (ITk), to operate under higher occupancy (instantaneous luminosity $7.5 \times 10^{34}\;\rm s^{-1}cm^{-2}$, which correspond to 200 inelastic pp collisions per bunch crossing) and radiation damage (fluence $2\times10^{16}\;\rm n_{eq}/cm^2$). …”
Publicado 2023
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4486por Shea, Owen“…The presentation will give details on the mechanics designs of the upgrade trackers. The design principles will be shown with examples realized in prototyping. …”
Publicado 2023
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4487por Yang, Zishuo“…The second topic of this dissertation is the development of readout electronics for a new silicon-strip tracking detector, the Upstream Tracker, to upgrade the LHCb detector. The upgraded LHCb detector will collect much more data in the upcoming runs of the Large Hadron Collider.…”
Publicado 2023
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4488por Terlizzi, Livia“…During the Long Shutdown 2 (LS2) of LHC, ALICE underwent a major upgrade of its apparatus, in view of the LHC Run 3 started in 2022, in which the experiment is operated at a larger-than-ever luminosity. …”
Publicado 2023
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4489por Biino, Cristina“…The CMS detector is therefore undergoing an extensive upgrade program to prepare for these demanding conditions. …”
Publicado 2022
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Enlace del recurso
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4490“…The operation of CMS at the HL-LHC requires an upgrade of the readout electronics. These new modern micro-electronics require power at precise voltages between 1.2 V and 2.5 V. …”
Enlace del recurso
Enlace del recurso
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4491por Dyks, Luke Aidan“…The benefits of these upgrades are explored in simulation, demonstrating that they would allow the production of shorter bunches, with lower energy spread, and lower emittance. …”
Publicado 2023
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4492por Van De Wall, Evan Richard“…This thesis highlights the development and design of the Type-0 electrical services for the all-new ITk Pixel tracking system that will lie at the heart of the upgraded ATLAS detector.…”
Publicado 2023
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4493por Budhiraju, Srinidhi“…The main objective of this project is to study the tau candidate particles in L1Calo to improve the tau identification in the L1Calo trigger system for the phase-1 upgrades in ATLAS. This is done by exploring the matching efficiency algorithm and studying the rCore energy.…”
Publicado 2023
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4494por Shea, Owen“…The pixel tracking detectors in the ATLAS and CMS experiments are scheduled to be replaced with upgraded versions during the next long shutdown period at the LHC. …”
Publicado 2023
Enlace del recurso
Enlace del recurso
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4495
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4496por Qian, Weiming“…The baseline architecture for the ATLAS Phase-II upgrade has a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency. …”
Publicado 2023
Enlace del recurso
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4497
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4498
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4499por Hedges, S J, Allen, N, Dervan, P J, McKemey, A K, Watts, S, Harton, J, Smy, M B, Hertzbach, S S, Kofler, R R, Strauss, M, Trandafir, A I, Burrows, P N, Dong, D, Kendall, H W, Lia, V, Osborne, L, Ross, D, Taylor, F, Verdier, R, Bashindzhagian, G L, Karmanov, D E, Merkin, M, Damerell, C, English, R, Gillman, A R, Jackson, D, Lintern, A L, Tappern, G J, Breidenbach, M, Crawford, G, Haller, G, Hildreth, M D, Höflich, J, Huffer, M E, Jaros, J A, Skarpaas, K V, Dong, Su, Abe, K, Hasuko, K, Nagamine, T, Suekane, F, Yuta, H, Arodzero, A, Brau, J E, Frey, R, Huber, J, Sinev, N B, Weiss, E, Serbo, V, Zapalac, G H, Baltay, C, Liu, M, Manly, S L, Snyder, J A, Emmet, W, Sinnott, J, Wandersee, AEnlace del recurso
Publicado 1995
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4500