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Mostrando 361 - 380 Resultados de 392 Para Buscar '"VLSI"', tiempo de consulta: 0.28s Limitar resultados
  1. 361
    “…PyNN is such an interface, making it possible to write a simulation script once, using the Python programming language, and run it without modification on any supported simulator (currently NEURON, NEST, PCSIM, Brian and the Heidelberg VLSI neuromorphic hardware). PyNN increases the productivity of neuronal network modelling by providing high-level abstraction, by promoting code sharing and reuse, and by providing a foundation for simulator-agnostic analysis, visualization and data-management tools. …”
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    PyNN: A Common Interface for Neuronal Network Simulators
  2. 362
    “…In particular, this paper details the innovative Very Large Scale Integration (VLSI) sensing layout, the accurate assembly fabrication process, the innovative, new fast read-out interface, as well as the auto-adaptive dynamic response of the CurvACE sensor. …”
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    Online Artículo Texto
    Hardware Architecture and Cutting-Edge Assembly Process of a Tiny Curved Compound Eye
  3. 363
    por Chen, Chun-Chi, Chen, Chao-Lieh, Lin, Yi
    Publicado 2016
    “…The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.…”
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    Online Artículo Texto
    All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement
  4. 364
    “…Neuromorphic Very Large Scale Integration (VLSI) devices emulate the activation dynamics of biological neuronal networks using either mixed-signal analog/digital or purely digital electronic circuits. …”
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    Online Artículo Texto
    Organizing Sequential Memory in a Neuromorphic Device Using Dynamic Neural Fields
  5. 365
    “…Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². …”
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    Online Artículo Texto
    Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration
  6. 366
    “…Increase in the number of electrode pairs improved the voltage generation, which suggested that the MEH had potential for microscale-very-large-scale-integration (μ-VLSI). The combined effects of ECPV, LSPR, and SP in the MEH could show an efficiency ∼2.5%, which was one of the highest ones reported, for Schottky-junction energy harvesters. …”
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    Online Artículo Texto
    Microfluidic Schottky-junction photovoltaics with superior efficiency stimulated by plasmonic nanoparticles and streaming potential
  7. 367
    por Micelli, A, Helle, K, Sandaker, H, Stugu, B, Barbero, M, Hugging, F, Karagounis, M, Kostyukhin, V, Kruger, H, Tsung, J W, Wermes, N, Capua, M, Fazio, S, Mastroberardino, A, Susinno, G, Gallrapp, C, Di Girolamo, B, Dobos, D, La Rosa, A, Pernegger, H, Roe, S, Slavicek, T, Pospisil, S, Jakobs, K, Kohler, M, Parzefall, U, Darbo, G, Gariano, G, Gemme, C, Rovani, A, Ruscino, E, Butter, C, Bates, R, Oshea, V, Parker, S, Cavalli-Sforza, M, Grinstein, S, Korokolov, I, Pradilla, C, Einsweiler, K, Garcia-Sciveres, M, Borri, M, Da Via, C, Freestone, J, Kolya, S, Lai, C H, Nellist, C, Pater, J, Thompson, R, Watts, S J, Hoeferkamp, M, Seidel, S, Bolle, E, Gjersdal, H, Sjobaek, K N, Stapnes, S, Rohne, O, Su, D, Young, C, Hansson, P, Grenier, P, Hasi, J, Kenney, C, Kocian, M, Jackson, P, Silverstein, D, Davetak, H, DeWilde, B, Tsybychev, D, Dalla Betta, G F, Gabos, P, Povoli, M, Cobal, M, Giordani, M P, Selmi, L, Cristofoli, A, Esseni, D, Palestri, P, Fleta, C, Lozano, M, Pellegrini, G, Boscardin, M, Bagolini, A, Piemonte, C, Ronchin, S, Zorzi, N, Hansen, T E, Hansen, T, Kok, A, Lietaer, N, Kalliopuska, J, Oja, A
    Publicado 2010
    “…To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology is an innovative combination of very-large-scale integration (VLSI) and Micro-Electro-Mechanical-Systems (MEMS) where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. …”
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    3D-FBK Pixel sensors: recent beam tests results with irradiated devices
  8. 368
    por Annovi, A
    Publicado 2011
    “…Andreani et al., The Fast Tracker Real Time Processor and Its Impact on Muon Isolation, Tau and b-Jet Online Selections at ATLAS, Conference Record 17th IEEE NPSS Real Time Conference Record of the 17th Real Time Conference, Lisbon, Portugal, 24 - 28 May 2010. [2] A. Annovi et al., A VLSI Processor for Fast Track Finding Based on Content Addressable Memories, IEEE Trans. …”
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    The Fast Tracker Real Time Processor
  9. 369
    “…Radiation Theory and Antenna; Cryptography; Quantum and Non-Linear Optics, Opto-Electronic Devices; Non-Linear Waveguides; Micro-Electronics and VLSI; Interdisciplinary.…”
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    3rd International Conference on Opto-Electronics and Applied Optics
  10. 370
    “…Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. …”
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    Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch
  11. 371
    “…The proposed design was successfully tested with a FPGA verification board. The VLSI architecture of this work contains 7.67-K gate counts and consumes the power of 5.8 mW or 1.9 mW at 100 MHz or 133 MHz processing rate using a TSMC 0.18 μm or 0.13 μm CMOS process. …”
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    Online Artículo Texto
    An Efficient Micro Control Unit with a Reconfigurable Filter Design for Wireless Body Sensor Networks (WBSNs)
  12. 372
    “…In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. …”
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    Online Artículo Texto
    A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses
  13. 373
    “…In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. …”
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    Online Artículo Texto
    Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms
  14. 374
    “…With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. …”
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    Online Artículo Texto
    A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique
  15. 375
    “…Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10(11) neuron based) large neural networks.…”
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    Online Artículo Texto
    Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET
  16. 376
    “…With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. …”
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    Online Artículo Texto
    Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique
  17. 377
    “…Particularly, the use of memristive devices in VLSI analogue concepts provides a promising pathway to realize novel bio-inspired computing architectures, which are able to unravel the foreseen difficulties of traditional electronics. …”
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    Online Artículo Texto
    Unsupervised Hebbian learning experimentally realized with analogue memristive crossbar arrays
  18. 378
    por Kazemi, Mohammad, Bocko, Mark F.
    Publicado 2019
    “…The proposed design principles are essential for design and implementation of very-large-scale-integration (VLSI) systems that provide high performance operation with low power consumption.…”
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    Online Artículo Texto
    Design rules for scalability in spin-orbit electronics
  19. 379
    “…A significant increase in the sensing response (~24%) at low operating temperature (100°C) opens the possibility of developing very large-scale integrable (VLSI), low operational cost gas sensors with easy fabrication methods and low-cost materials.…”
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    Nitrogen-Doped Carbon Dots Induced Enhancement in CO(2) Sensing Response From ZnO–Porous Silicon Hybrid Structure
  20. 380
    “…Vision chips inspired by the LGMD have been successfully implemented in very-large-scale-integration (VLSI) system. However, transistor-based chips and single devices to simulate LGMD neurons make them bulky, energy-inefficient and complicated. …”
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    Memristor-based biomimetic compound eye for real-time collision detection
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