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Mostrando 381 - 392 Resultados de 392 Para Buscar '"VLSI"', tiempo de consulta: 0.19s Limitar resultados
  1. 381
    por Seçkiner, Soner, Köse, Selçuk
    Publicado 2022
    “…Due to the highly sophisticated interactions in modern VLSI circuits, the interactions among multiple masking shares are quite challenging to model and thus information leakage from one share to another through noise coupling is difficult to mitigate. …”
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    Online Artículo Texto
    Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking
  2. 382
    por Giannetti, P, Annovi, A, Crescioli, F
    Publicado 2011
    “…Andreani et al., The FastTracker Real Time Processor and Its Impact on Muon Isolation, Tau and b-Jet Online Selections at ATLAS, Conference Record 17th IEEE NPSS Real Time Conference Record of the 17th Real Time Conference, Lisbon, Portugal, 24 - 28 May 2010. [2] A. Annovi et al., "A VLSI Processor for Fast Track Finding Based on Content Addressable Memories ", IEEE Trans. …”
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    The Fast Tracker Real Time Processor and Its Impact on the Muon Isolation, Tau amp; b-Jet Online Selections at ATLAS
  3. 383
    por Davis, R, Gingrich, D M, Pinfold, J L, Rodning, N L, Boos, E, Zhautykov, B O, Aubert, Bernard, Bazan, A, Beaugiraud, B, Boniface, J, Colas, Jacques, Eynard, G, Jézéquel, S, Le Flour, T, Linossier, O, Nicoleau, S, Rival, F, Sauvage, G, Thion, J, Van den Plas, D, Wingerter-Seez, I, Zitoun, R, Zolnierowski, Y, Chmeissani, M, Fernández, E, Garrido, L, Martínez, M, Padilla, C, Gordon, H A, Radeka, V, Rahm, David Charles, Stephani, D, Baisin, L, Berset, J C, Chevalley, J L, Gianotti, F, Gildemeister, O, Marin, C P, Nessi, Marzio, Poggioli, Luc, Richter, W, Vuillemin, V, Baze, J M, Gosset, L G, Lavocat, P, Lottin, J P, Mansoulié, B, Meyer, J P, Renardy, J F, Schwindling, J, Teiger, J, Collot, J, de Saintignon, P, Dzahini, D, Hostachy, J Y, Hoummada, A, Laborie, G, Mahout, G, Hervás, L, Chekhtman, A, Cousinou, M C, Dargent, P, Dinkespiler, B, Etienne, F, Fassnacht, P, Fouchez, D, Martin, L, Miotto, A, Monnier, E, Nagy, E, Olivetto, C, Tisserant, S, Battistoni, G, Camin, D V, Cavalli, D, Costa, G, Cozzi, L, Fedyakin, N N, Ferrari, A, Mandelli, L, Mazzanti, M, Perini, L, Resconi, S, Sala, P R, Beaudoin, G, Depommier, P, León-Florián, E, Leroy, C, Roy, P, Augé, E, Chase, Robert L, Chollet, J C, de La Taille, C, Fayard, Louis, Fournier, D, Hrisoho, A T, Merkel, B, Noppe, J M, Parrour, G, Pétroff, P, Schaffer, A C, Seguin-Moreau, N, Serin, L, Tisserand, V, Vichou, I, Canton, B, David, J, Genat, J F, Imbault, D, Le Dortz, O, Savoy-Navarro, Aurore, Schwemling, P, Eek, L O, Lund-Jensen, B, Söderqvist, J, Lefebvre, M, Robertson, S
    Publicado 1996
    “…A prototype covering approximately 0.8 in pseudo-rapidity and 9 degrees in azimuth was built and tested at CERN in July 94. CMOS and GaAs VLSI preamplifiers were designed and tested for this occasion. …”
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    Construction and test of a fine-grained liquid argon preshower prototype
  4. 384
    “…The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). …”
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    Online Artículo Texto
    CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor
  5. 385
    “…Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. …”
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    Online Artículo Texto
    Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing
  6. 386
    “…The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. …”
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    A high performance cost-effective digital complex correlator for an X-band polarimetry survey
  7. 387
    “…Under the same condition, the integration of ten such μ-DropFCs could produce a power density of ∼7 mW cm(−2) at an efficiency of 3.4%, showing the potential of the prototype for a very large scale integration (VLSI). The μ-DropFC could also degrade ∼85% of an industrial pollutant, rhodamine 6G, in 1 h while generating a power density of ∼0.6 mW cm(−2). …”
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    Microdroplet photofuel cells to harvest high-density energy and dye degradation
  8. 388
    “…In addition, the postsynaptic currents of the channel directly connect to the very large scale integration (VLSI) implementation of the LIF mode that can convert high-frequency information into spare pulses based on the threshold of membrane potential. …”
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    Synaptic transistor with multiple biological functions based on metal-organic frameworks combined with the LIF model of a spiking neural network to recognize temporal information
  9. 389
    “…This is the case for the outer detector regions of ATLAS, CMS and LHC-B, such as muons, outer regions of the calorimeters and trackers, and the whole ALICE detector. Emerging commercial VLSI deep submicron CMOS processes have a very thin gate oxide of 10~nm or less, and therefore submicron devices are expected to become intrinsically hardened against charge trapping effects in the thin oxides. …”
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    Studying Radiation Tolerant ICs for LHC
  10. 390
    por Deplano, C
    Publicado 2006
    “…In the Muon System there are 7632 DIALOG and 3552 SYNC devices. DIALOG and SYNC are VLSI (Very Large Scale Integration) circuits and were designed in Cagliari by the LHCb group. …”
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    Instruments for calibration and monitoring of the LHCb Muon Detector
  11. 391
    por Hussain, Shaista, Basu, Arindam
    Publicado 2016
    “…We also present results of applying our algorithm to classify the MNIST-DVS dataset collected from a real spike-based image sensor and show results comparable to the best reported ones (88.1% accuracy). For VLSI implementations, we show that the reduced synaptic memory can save upto 4X area compared to conventional crossbar topologies. …”
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    Multiclass Classification by Adaptive Network of Dendritic Neurons with Binary Synapses Using Structural Plasticity
  12. 392
    por Pal, Sanjoy
    Publicado 2012
    “…This readout electronics has been implemented on a 16 channel mixed signal VLSI chip named MANAS. A large number of validation tests were carried out on the first and the second production batches during April to August, 2005 to ensure satisfactory performance of MANAS. …”
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    Characterizations of Cathode pad chamber as tracking detector for MUON Spectrometer of ALICE
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