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761“…This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. …”
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762
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763“…This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly. …”
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764por Menouni, M, Arutinov, D, Backhaus, M, Barbero, M, Beccherle, R, Breugnon, P, Caminada, L, Dube, S, Darbo, G, Fleury, J, Fougeron, D, Garcia-Sciveres, M, Gensolen, F, Gnani, D, Gonella, L, Gromov, V, Hemperek, T, Jensen, F, karagounis, M, Kluit, R, Krüger, G, Kruth, A, Lu, Y, Mekkaoui, A, Rozanov, A, Schipper, J.D, Zivkovic, V“…The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. …”
Publicado 2013
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info:eu-repo/semantics/article -
765“…This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. …”
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766por Augustin, Heiko, Berger, Niklaus, Dittmeier, Sebastian, Grzesik, Carsten, Hammerich, Jan, Huang, Qinhua, Huth, Lennart, Kiehn, Moritz, Kozlinskiy, Alexandr, Meier Aeschbacher, Frank, Perić, Ivan, Perrevoort, Ann-Kathrin, Schöning, André, Shrestha, Shruti, vom Bruch, Dorothea, Wauters, Frederik, Wiedner, Dirk“…The observed efficiency of the MuPix7 chip including the full readout system is $\geq99\%$ in a high rate test beam.…”
Publicado 2016
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767
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768por Campbell, M, Alozy, J., Ballabriga, R., Frojdh, E., Heijne, E., Llopart, X., Poikela, T., Tlustos, L., Valerio, P., Wong, W.“…The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. …”
Publicado 2016
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769
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770
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771por Casanova Mohr, R., Cavallaro, E., Föster, F., Grinstein, S., Peric, I., Puigdengoles, C., Terzo, S., Vilella, E.“…The H35DEMO chip is a HV/HR-MAPS demonstrator of 18.49 mm x 24.4 mm, fabricated with a 0.35 µm HVCMOS process from AMS in four different substrate resistivities. …”
Publicado 2019
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info:eu-repo/semantics/article -
772
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773por Werran, Dustin Connor“…New hardware is being developed for this upgrade, and a test chip called the RD53A has been created as a prototype version of that future hardware. …”
Publicado 2019
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774por Campbell, Michael“…The Medipix and Timepix readout chips are used in classrooms, at synchrotron light sources, as mixed field radiation monitors on the International Space Station and in many other applications. …”
Publicado 2019
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775
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776
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777por Emriskova, Natalia“…For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with a 50\,$\mu$m $\times$ 50\,$\mu$m pixel size, is being designed in 65 nm CMOS technology by the RD53 collaboration. …”
Publicado 2019
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778por Menouni, Mohsine, Barrillon, Pierre, Flores, Leyre, Fougeron, Denis, Hemperek, Tomasz, Joly, Eva, Lalic, Jelena, Strebler, Thomas“…The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. …”
Publicado 2022
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779
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780