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301por Kimura, N“…The triggering in the ATLAS detector is realized using a three level trigger approach, in which the first level (L1) is hardware based and the second (L2) and third (EF) stag are realized using large computing farms. …”
Publicado 2012
Enlace del recurso
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302por Kimura, N“…The triggering in the ATLAS detector is realized using a three level trigger approach, in which the first level (Level-1) is hardware based and the second (Level-2) and third (EF) stag are realized using large computing farms. …”
Publicado 2012
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303por Saa Hernandez, A., Andersson, A., Breunlin, J., Milas, N., Rohrer, M., Streun, A., Schlott, V.Enlace del recurso
Publicado 2013
info:eu-repo/semantics/article -
304
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305por Lipiansky, Ed“…The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. …”
Publicado 2012
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306“…This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. …”
Enlace del recurso
Enlace del recurso
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307
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308por Zhang, J“…This will be performing by track reconstruction using hardware with massive parallelism using associative memories (AM) and FPGAs. …”
Publicado 2014
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309por Alison, J, Ancu, L, Anderson, J, Andreani, A, Andreazza, A, Annovi, A, Antonelli, M, Atkinson, M, Auerbach, B, Baines, J, Barberio, E, Beccherle, R, Beretta, M, Biesuz, N V, Blair, R, Blazey, G, Bogdan, M, Boveia, A, Britzger, D, Bryant, P, Burghgrave, B, Calderini, G, Cavaliere, V, Cavasinni, V, Chakraborty, D, Chang, P, Cheng, Y, Cipriani, R, Citraro, S, Citterio, M, Crescioli, F, Dell'Orso, M, Donati, S, Dondero, P, Drake, G, Gadomski, S, Gatta, M, Gentsos, C, Giannetti, P, Giulini, M, Gkaitatzis, S, Howarth, J W, Iizawa, T, Kapliy, A, Kasten, M, Kim, Y K, Kimura, N, Klimkovich, T, Kordas, K, Korikawa, T, Krizka, K, Kubota, T, Lanza, A, Lasagni, F, Liberali, V, Li, H L, Love, J, Luciano, P, Luongo, C, Magalotti, D, Melachrinos, C, Meroni, C, Mitani, T, Negri, A, Neroutsos, P, Neubauer, M, Nikolaidis, S, Okumura, Y, Pandini, C, Penning, B, Petridou, C, Piendibene, M, Proudfoot, J, Rados, P, Roda, C, Rossi, E, Sakurai, Y, Sampsonidis, D, Sampsonidou, D, Schmitt, S, Schoening, A, Shochet, M, Shojaii, S, Soltveit, H, Sotiropoulou, C L, Stabile, A, Tang, F, Testa, M, Tompkins, L, Vercesi, V, Villa, M, Volpi, G, Webster, J, Wu, X, Yorita, K, Yurkewicz, A, Zeng, J C, Zhang, J“…This will perform track reconstruction using hardware with massive parallelism using associative memories and FPGAs. …”
Publicado 2014
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310por Pandini, Carlo Enrico“…The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. …”
Publicado 2015
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311por Stramaglia, Maria Elena“…The hardware is supported by an embedded software stack running on the read-out boards. …”
Publicado 2015
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312por Dr. Matveev, Zakhar A.“…The gap (often 2 orders of magnitude) between modernized workloads and unoptimized baselines is increasing with every next hardware generation. <p style="text-align: justify;"> SIMD code modernization is not without cost, but exciting new features of OpenMP 4.0 "explicit vectorization" and new Intel® "Vectorization Advisor" software tool make it possible to introduce efficient and portable SIMD parallelism without disrupting ongoing development. …”
Publicado 2015
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313
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314por Stramaglia, Maria Elena“…The hardware is supported by an embedded software stack running on the read-out boards. …”
Publicado 2015
Enlace del recurso
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