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401
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402por Charlet, D“…The SPECS is a single master, multi slave serial bus. It communicates between an unique master and up to 32 slaves (limit fixed by the address range), at a 10 MHz rate, thanks to 4 different unidirectional lines.…”
Publicado 2007
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404por Gong, Datao, Hou, Suen, Liang, Zhihua, Liu, Chonghan, Liu, Tiankuan, Da-Shun Su, Teng, Ping-Kun, Xiang, Annie C, Ye, Jingbo“…Based on a commercial 0.25 μm silicon-onsapphire CMOS technology, we design a 16:1 serializer with 5 Gbps serial data rate. This ASIC has been submitted for fabrication. …”
Publicado 2009
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405por Gong, D“…A high speed, low power 16:1 serializer is developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. …”
Publicado 2010
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406por Gong, D“…A high speed, low power 16:1 serializer has been developed with a commercial 0.25 μm silicon-on-sapphire CMOS technology. …”
Publicado 2010
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407por Gonella, L, Arutinov, D, Barbero, M, Eyring, A, Hügging, F, Karagounis, M, Krüger , H, Wermes, N“…Powering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. …”
Publicado 2010
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408por Andreani, A, Annovi, A, Beccherle, R, Beretta, M, Cipriani, R, Citraro, S, Citterio, M, Colombo, A, Crescioli, F, Dimas, D, Donati, S, Giannetti, P, Kordas, K, Lanza, A, Liberali, V, Luciano, P, Magalotti, D, Neroutsos, P, Nikolaidis, S, Piendibene, M, Sakellariou, A, Shojaii, S, Sotiropoulou, C-L, Stabile, A“…The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. …”
Publicado 2014
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409“…This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. …”
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410por Biesuz, Nicolo Vladi, Citraro, Saverio, Luciano, Pierluigi, Magalotti, Daniel, Rossi, Enrico“…The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. …”
Publicado 2015
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411por Biesuz, Nicolo Vladi, Citraro, Saverio, Luciano, Pierluigi, Magalotti, Daniel, Rossi, Enrico“…The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. …”
Publicado 2015
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412por Wang, Jinhong, Guan, Liang, Sang, Ziru, Chapman, J.W., Dai, Tiesheng, Zhou, Bing, Zhu, Junjie“…We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. …”
Publicado 2015
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413
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417por Fischer, A.“…Photo 6 - Mechanical acceptance tests for HEC serial modules at CERN. Photo 7 - Mechanical acceptance tests for HEC serial modules at CERN. …”
Publicado 2001
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418por Anagnostou, G, Bright-Thomas, P G, Garvey, J, Staley, R J, Stokes, W N, Talbot, S D, Watkins, P M, Watson, A, Achenbach, R, Hanke, P, Husmann, D, Keller, M, Kluge, E E, Krause, J, Mahboubi, K, Megele, R, Meier, K, Pfeiffer, U, Schatz, V, Schmitt, K, Schumacher, C, Stelzer, B, Stelzer, O, Stock, P, Ulses, E, Bauss, B, Jakobs, K, Schäfer, U, Thomas, J, Eisenhandler, Eric F, Gibson, W R, Landon, M P J, Barnett, B M, Brawn, I P, Edwards, J, Gee, C N P, Gillman, A R, Hatley, R, Jayananda, K, Perera, V J O, Shah, A A, Shah, T P, Bohm, C, Engström, M, Hellman, S, Silverstein, SEnlace del recurso
Publicado 2000
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