“…The Compact Muon Solenoid (CMS) detector is introduced, with particular emphasis on the calorimeters, and the trigger and data acquisition system. An FPGA-based sort processor for use in the CMS Global Calorimeter Trigger has been designed. …”
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“…In the present run of the LHC, CMS data reconstruction and simulation algorithms benefit greatly from being executed as multiple threads running on several processor cores. …”
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“…The program, entitled "Innovative and Novel Computational Impact on Theory and Experiment" will award a total of 4.5 million supercomputer processor hours and 100 trillion bytes of data storage space at the National Energy Research Scientific Computing Center at DOE's Lawrence Berkeley National Laboratory (1 page).…”
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“…The aim of the test was to send RoI information from the CPROD to the RoIB and ROS systems, and to understand the hardware interface between the systems concentrating on data performance and data integrity. The systems were controlled and monitored by separate diagnostic programs, and software integration within the ATLAS online framework was not included in the goals of these tests.…”
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“…With no need to change the implemented algorithms, the processing time can be approximately reduced N-fold, N being the number of available processor cores. CONCLUSION: R/parallel saves bioinformaticians time in their daily tasks of analyzing experimental data. …”
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“…The TRTViewer is the dedicated program for monitoring the TRT raw data quality and detector performance at different hardware levels: individual straws, readout chips and electronic boards. …”
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“…Motivation: Next-generation DNA sequencing machines are generating an enormous amount of sequence data, placing unprecedented demands on traditional single-processor read-mapping algorithms. …”
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“…This fully-revised edition includes the latest enhancements in OpenCL 2.0 including: Shared virtual memory to increase programming flexibility and reduce data transfers that consume resources Dynamic parallelism which reduces processor load and avoids bottlenecks Improved imaging support and integration with OpenGL  Designed to work on multiple platfor…”
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“…One of the upgrades for the trigger system is the Global Feature Extractor (gFEX) which aims to recover lost efficiency in boosted hadronic final states by identifying large radius jets produced by top quarks, Higgs, Z and W bosons which are critical for future ATLAS physics programs. This module is a unique board with 3 processor FPGAs for data processing and an embedded multi-processor system-on-chip for slow-control and monitoring. …”
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“…</p> <p><u>Lecturer's Short Bio:</u>&nbsp;Sverre Jarp worked in the IT Department at CERN for over 40 years and held multiple managerial and technical positions promoting advanced but cost-effective, large-scale computing and data management solutions for the Laboratory. Today, as honorary staff at CERN, he retains an unabated interest in several IT areas, in particular processor architecture related to the domains of Big Data and High Throughput Computing as well as application scalability based on vector- and parallel-programming. …”
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“…It provides hardware-isolated area called a trusted execution environment (TEE) in the processor for sensitive data and code. This paper demonstrates a vulnerability in the secure world in the form of a cross-world, secure world to normal world, covert channel. …”
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“…The ATLAS L1 Topological trigger uses physically motivated kinematic quantities of triggered candidates to reject undesired background processes extending the reach of the ATLAS physics program. The Central Trigger Processor, heart of the ATLAS L1 Trigger system, was also upgraded. …”
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“…We will present how we intend to use new services and infrastructure to provide more efficient and transparent access to the data. We will discuss the computing plans to make better use of the computing capacity by scheduling more of the processor nodes, making better use of the disk storage, and more intelligent use of the networking.…”
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“…The talk presents preliminary details of the hardware design program.…”
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“…It is used for time critical applications within the front-end part of the DAQ system, mainly to exchange data control messages between I/O processors. Key objectives of the design were low message overheads, efficient use of the data transfer buses, provision of broadcast functionality and a hardware and operating system independent implementation of the application interface. …”
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“…The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the High Level Trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. …”
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“…The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the High Level Trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. …”
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“…We discuss the impact of these technologies on the art of programming, the data centres of the future and daily life. …”
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“…After two years of remarkable performance from the LHC and ATLAS, the experiment has accumulated more than 25 fb-1 of data. The total volume of beam and simulated data products exceeds 100 PB distributed across more than 150 computing centers around the world, managed by the experiment's distributed data management system. …”
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“…The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the High Level Trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. …”
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