PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors

This paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, pow...

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Detalles Bibliográficos
Autores principales: Aspell, P, Barney, D, Bialas, W, Bloch, P, Dupanloup, M, Go A, Kloukinas, K, Manthos, N, Moraes, D, Morrissey, Q, Peisert, Anna, Reynaud, S, Sidiropoulos, G, Tcheremoukhine, A, Vichoudis, P
Lenguaje:eng
Publicado: 2006
Materias:
Detectors and Experimental Techniques
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/1014261
Descripción
Sumario:This paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, power consumption and radiation tolerance with respect to total ionizing dose and robustness to single event upsets (SEU).

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