PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors

This paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, pow...

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Detalles Bibliográficos
Autores principales: Aspell, P, Barney, D, Bialas, W, Bloch, P, Dupanloup, M, Go A, Kloukinas, K, Manthos, N, Moraes, D, Morrissey, Q, Peisert, Anna, Reynaud, S, Sidiropoulos, G, Tcheremoukhine, A, Vichoudis, P
Lenguaje:eng
Publicado: 2006
Materias:
Detectors and Experimental Techniques
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/1014261
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author Aspell, P
Barney, D
Bialas, W
Bloch, P
Dupanloup, M
Go A
Kloukinas, K
Manthos, N
Moraes, D
Morrissey, Q
Peisert, Anna
Reynaud, S
Sidiropoulos, G
Tcheremoukhine, A
Vichoudis, P
author_facet Aspell, P
Barney, D
Bialas, W
Bloch, P
Dupanloup, M
Go A
Kloukinas, K
Manthos, N
Moraes, D
Morrissey, Q
Peisert, Anna
Reynaud, S
Sidiropoulos, G
Tcheremoukhine, A
Vichoudis, P
author_sort Aspell, P
collection CERN
description This paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, power consumption and radiation tolerance with respect to total ionizing dose and robustness to single event upsets (SEU).
id cern-1014261
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2006
record_format invenio
spelling cern-10142612019-09-30T06:29:59Zhttp://cds.cern.ch/record/1014261engAspell, PBarney, DBialas, WBloch, PDupanloup, MGo AKloukinas, KManthos, NMoraes, DMorrissey, QPeisert, AnnaReynaud, SSidiropoulos, GTcheremoukhine, AVichoudis, PPACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensorsDetectors and Experimental TechniquesAccelerators and Storage RingsThis paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, power consumption and radiation tolerance with respect to total ionizing dose and robustness to single event upsets (SEU).oai:cds.cern.ch:10142612006
spellingShingle Detectors and Experimental Techniques
Accelerators and Storage Rings
Aspell, P
Barney, D
Bialas, W
Bloch, P
Dupanloup, M
Go A
Kloukinas, K
Manthos, N
Moraes, D
Morrissey, Q
Peisert, Anna
Reynaud, S
Sidiropoulos, G
Tcheremoukhine, A
Vichoudis, P
PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title_full PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title_fullStr PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title_full_unstemmed PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title_short PACE3: a large dynamic range analog memory front-end ASIC assembly for the charge readout of silicon sensors
title_sort pace3: a large dynamic range analog memory front-end asic assembly for the charge readout of silicon sensors
topic Detectors and Experimental Techniques
Accelerators and Storage Rings
url http://cds.cern.ch/record/1014261
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