A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated...

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Detalles Bibliográficos
Autores principales: Dahoumane, M, Dzahini, D, Bouvier, J, Lagorio, E, Hostachy, J Y, Gallin-Martel, L, Rossetto, O, Hu, Y, Ghazlane, H, Dallet, D
Lenguaje:eng
Publicado: CERN 2007
Materias:
Accelerators and Storage Rings
Acceso en línea:https://dx.doi.org/10.5170/CERN-2007-007.326
http://cds.cern.ch/record/1091473

Internet

https://dx.doi.org/10.5170/CERN-2007-007.326
http://cds.cern.ch/record/1091473

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