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A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 3...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2008
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2008-008.459 http://cds.cern.ch/record/1159551 |