A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 3...

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Detalles Bibliográficos
Autores principales: Mester, C, Paillard, C, Morira, P
Lenguaje:eng
Publicado: CERN 2008
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2008-008.459
http://cds.cern.ch/record/1159551
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author Mester, C
Paillard, C
Morira, P
author_facet Mester, C
Paillard, C
Morira, P
author_sort Mester, C
collection CERN
description A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2008
publisher CERN
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spelling cern-11595512019-09-30T06:29:59Zdoi:10.5170/CERN-2008-008.459http://cds.cern.ch/record/1159551engMester, CPaillard, CMorira, PA multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applicationsDetectors and Experimental TechniquesA multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.CERNoai:cds.cern.ch:11595512008
spellingShingle Detectors and Experimental Techniques
Mester, C
Paillard, C
Morira, P
A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title_full A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title_fullStr A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title_full_unstemmed A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title_short A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications
title_sort multi-channel 24.4 ps bin size time-to-digital converter for hep applications
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2008-008.459
http://cds.cern.ch/record/1159551
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AT morirap amultichannel244psbinsizetimetodigitalconverterforhepapplications
AT mesterc multichannel244psbinsizetimetodigitalconverterforhepapplications
AT paillardc multichannel244psbinsizetimetodigitalconverterforhepapplications
AT morirap multichannel244psbinsizetimetodigitalconverterforhepapplications

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