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The algorithm for FIR corrections of the VELO analogue links and its performance

The data from the VELO front-end is sent to the ADCs on the read-out board over a serial analogue link. Due imperfections in the link, inter-symbol cross talk occurs between adjacent time-bins in the transfer. This is corrected by an FIR filter implemented in the pre-processing FPGA locacted on the...

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Detalles Bibliográficos
Autores principales: Akiba, K, Borel, J, Buytaert, J, Eklund, L, Gersabeck, M
Lenguaje:eng
Publicado: 2007
Materias:
Acceso en línea:http://cds.cern.ch/record/1205588