The algorithm for FIR corrections of the VELO analogue links and its performance

The data from the VELO front-end is sent to the ADCs on the read-out board over a serial analogue link. Due imperfections in the link, inter-symbol cross talk occurs between adjacent time-bins in the transfer. This is corrected by an FIR filter implemented in the pre-processing FPGA locacted on the read-out board. This note reports on a method to determine the coefficients for the filter using date taken in-situ. Simulations are presented that show the performance of the methods as it is implemented in the LHCb read-out board. The effectiveness of the algorithm is demonstrated by the improvements in tracking performance on beam test data it brings.