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The algorithm for FIR corrections of the VELO analogue links and its performance
The data from the VELO front-end is sent to the ADCs on the read-out board over a serial analogue link. Due imperfections in the link, inter-symbol cross talk occurs between adjacent time-bins in the transfer. This is corrected by an FIR filter implemented in the pre-processing FPGA locacted on the...
| Autores principales: | , , , , |
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| Lenguaje: | eng |
| Publicado: |
2007
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1205588 |