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A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter c...
| Autores principales: | , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2009
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.533 http://cds.cern.ch/record/1235877 |