A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout

The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter c...

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Detalles Bibliográficos
Autores principales: Rarbi, F, Dzahini, D, Gallin-Martell, L, Hostachy, J Y
Lenguaje:eng
Publicado: CERN 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.533
http://cds.cern.ch/record/1235877
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author Rarbi, F
Dzahini, D
Gallin-Martell, L
Hostachy, J Y
author_facet Rarbi, F
Dzahini, D
Gallin-Martell, L
Hostachy, J Y
author_sort Rarbi, F
collection CERN
description The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000).
id cern-1235877
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
record_format invenio
spelling cern-12358772019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.533http://cds.cern.ch/record/1235877engRarbi, FDzahini, DGallin-Martell, LHostachy, J YA Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated ReadoutDetectors and Experimental TechniquesThe necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000).CERNoai:cds.cern.ch:12358772009
spellingShingle Detectors and Experimental Techniques
Rarbi, F
Dzahini, D
Gallin-Martell, L
Hostachy, J Y
A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title_full A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title_fullStr A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title_full_unstemmed A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title_short A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout
title_sort digitally calibrated 12 bits 25 ms/s pipelined adc with a 3 input multiplexer for calice integrated readout
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2009-006.533
http://cds.cern.ch/record/1235877
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