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On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)
In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz whi...
| Autores principales: | , , , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2009
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.543 http://cds.cern.ch/record/1235879 |